FIGS. 5(a) to 5(c) are diagrams illustrating a high electron mobility transistor (hereinafter referred to as HEMT) formed on an InP substrate included in a prior art semiconductor device, in which FIG. 5(a) is a top plan view and FIGS. 5(b) and 5(c) are sectional views taken along lines Vb--Vb and Vc--Vc of FIG. 5(a), respectively. In these figures, a mesa structure comprising compound semiconductor layers, i.e., an intrinsic (hereinafter referred to as i type) InAlAs buffer layer 2, an i type InGaAs channel layer 3, an i type InAlAs spacer layer 4, an n type InAlAs electron supply layer 5, an i type InAlAs Schottky formation layer 6, an n type InAlAs layer 7, and a low-resistance n type InGaAs contact layer 8 with carrier concentration of 2.times.10.sup.19 cm.sup.3, is disposed on a portion of the InP substrate 1. A recess 11 penetrates through the InGaAs contact layer 8 and the InAlAs layer 7 and reaches into the Schottky formation layer 6. A gate electrode 10 is disposed on the Schottky formation layer 6 in the bottom of the recess 11. Source and drain electrodes 9a and 9b are disposed on the mesa structure where the recess 11 is absent and extended onto portions of the substrate 1. Preferably, the i type InAlAs buffer layer 2 is 1000.about.1500 angstroms thick and each of the layers disposed on the buffer layer 2 is 100.about.400 angstroms thick. Source and drain regions are formed in the n type InAlAs layer 7. Reference numeral 10a designates a bonding pad at an end of the gate electrode 10, to which wires from external devices or devices disposed on other regions of the InP substrate 1 are bonded.
FIGS. 6(a) to 6(d) illustrate process steps in a method of producing the HEMT. In the figures, the same reference numerals as in FIGS. 5(a) to 5(c) designate the same or corresponding parts, and reference numeral 12 designates a photoresist pattern.
Initially, there are successively grown on the InP substrate 1, the i type InAlAs buffer layer 2, the i type InGaAs channel layer 3, the i type InAlAs spacer layer 4, the n type InAlAs electron supply layer 5, the i type InAlAs Schottky formation layer 6, the n type InAlAs layer 7, and the n type InGaAs contact layer 8, preferably by metal organic chemical vapor deposition (MOCVD). Then, a photoresist pattern 12 is formed on the n type InGaAs contact layer 8 by a conventional photolithographic technique. Using the photoresist pattern 12 as a mask, the semiconductor layers 2 to 8 are wet etched using tartaric acid or the like as an etchant to form the semiconductor layers 2 to 8 in a mesa shape as shown in FIG. 6(a). Thus, the mesa-shaped semiconductor layers are isolated from other regions on the InP substrate 1. Then, as shown in FIG. 6(b), the source and drain electrodes 9a and 9b are formed on prescribed regions on the n type InGaAs contact layer 8, extending onto the surface of the InP substrate 1. Then, recess etching is carried out from the surface of the contact layer 8 while measuring a current flowing between the source and drain electrodes 9a and 9b, whereby the thickness of the i type InAlAs Schottky formation layer 6 in a gate region is adjusted to a desired thickness, resulting the recess 11 shown in FIG. 6(c). Thereafter, the gate electrode 10 is formed on the i type InAlAs Schottky formation layer 6 exposed on the bottom of the recess 11 using a lift-off process.
In operation, when a bias voltage is applied between the source and drain electrodes 9a and 9b, a two-dimensional gas serving as a channel is formed in the i type InGaAs channel layer 3 in the vicinity of its boundary with the i type InAlAs spacer layer 4, and a current flows through the channel. This current is controlled by a voltage applied to the gate electrode 10 to operate the transistor.
In a semiconductor device produced by successively growing compound semiconductor layers on a semiconductor substrate and forming a device in a prescribed region of the compound semiconductor layers, like the above-described semiconductor device in which the HEMT is formed on the InP substrate, the thickness of the compound semiconductor layers must be larger than 0.2 micron. In addition, in a field effect transistor having a recessed gate, like the above-described HEMT, the thickness of semiconductor layers between the bottom of the recess, on which the gate electrode is formed, and the surface of the semiconductor substrate must be larger than 0.2 micron.
Therefore, in a structure as shown in FIG. 5(b), in which compound semiconductor layers on a semiconductor substrate are formed into a mesa by etching to isolate a device from other regions on the substrate, the difference in levels between the surface of the semiconductor substrate and the top of the mesa is more than 0.2 micron. In FIG. 5(b), since the HEMT includes the recessed gate, the difference in levels between the surface of the semiconductor substrate and the bottom of the recess is more than 0.2 micron. In this structure, when an electrode is formed on the surface of the mesa or on the bottom of the recess extending onto the surface of the substrate, a lift-off process is usually employed as described above. More specifically, a photoresist film is formed on the mesa and its periphery, and a prescribed portion of the photoresist film is opened by a photolithographic technique to form a mask pattern. Then, a metal for the electrode is deposited via the mask pattern, followed by removal of the mask pattern, resulting in an electrode.
In forming a photoresist pattern by the above-described photolithographic technique, a reducing projection exposure apparatus is generally used for the exposure process, and a resolution limit R of the reducing projection exposure apparatus is represented as follows: EQU R=k1 .lambda./NA (1)
where NA is a numerical aperture of a projection lens, .lambda. is the wavelength of the exposure light, and k1 is a constant indicating lens performance, which is 0.612 in a case of a spherical projection lens according to a theory by Rayleigh. It is known that it is possible to form a fine exposure pattern by increasing the numerical aperture (NA), according to the equation (1).
In forming a photoresist pattern on a substrate having a level difference of 0.2 micron or more, however, the depth of focus is reduced by increasing the numerical aperture (NA), resulting in an insufficient exposure intensity. This makes it very difficult to project a fine exposure pattern having constant light intensity on the substrate having a level difference of 0.2 micron or more. Therefore, in forming a photoresist pattern having an opening of 0.25 micron or below in width, a uniform width of the opening pattern is not obtained and the width also varies in a depth direction of the opening pattern. In this way, in forming the gate electrode 10 on the bottom surface of the recess 11 extending onto the surface of the InP substrate 1 in a lift-off process in the formation of the HEMT, if the opening of the photoresist pattern is fine-patterned in accordance with a desired gate electrode width of 0.25 micron or below, the resulting gate electrode is not uniform in its thickness and width and, in some cases, the gate electrode is discontinuous at the edge of the mesa structure, resulting in a HEMT with poor reliability.
It is thought that this problem may be avoided if the device is isolated by implanting ions into regions where the device is not formed so that the ions pentrate to the substrate. In the InP system HEMT with the n type InGaAs layer 8 for contacting with electrodes as an uppermost layer, however, the n type InGaAs layer is not insulated by ion implantation, so the HEMT is not completely isolated. When compositions of the respective compound semiconductor layers are determined so that these layers can be insulated by ion implantation, the compositions of the respective layers do not produce preferred device characteristics.